1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to a reconfigurable architecture, and more particularly, to efficiently processing an interrupt when an interrupt request occurs while a loop is executed in a coarse grained array.
2. Description of the Related Art
Traditionally, an apparatus performing an operation is embodied by hardware or software. For example, when a network controller performing a network interface is embodied on a computer chip, the network controller is able to perform only a network interface function defined during fabrication by a manufacturer. After the network controller is fabricated, it is not possible to change the function of the network controller. On the other hand, for example, a program for executing a desired function is programmed and the program is executed by a general purpose processor, thereby satisfying a purpose for a user. In the method of using software, a new function may be performed by changing the software after fabricating hardware in a factory. When software is used, various functions may be performed by using a given hardware but there is a drawback of a lower speed than when hardware is exclusively used.
To overcome the problem of the described method of using hardware and software, there is provided a reconfigurable architecture. The reconfigurable architecture can be customized to solve any problem, after device fabrication, and can exploit a large degree of spatially customized computation in order to perform their computation.
FIG. 1 is a diagram illustrating an example of a related art reconfigurable architecture. A plurality of arithmetic and logic units (ALUs) 101, 102, 103, 104, and 105 are connected a plurality of lines 106 to form a field programmable gate array (FPGA). The FPGA is configured to compute “A*x*x+B*X+C,” as an example. If the operation of “A*x*x+B*X+C” frequently occurs, an FPGA as shown in FIG. 1 is configured to perform the operation, thereby more quickly performing the operation than the method of using software. Also, a configuration of the FPGA may be changed by applying a current to the lines 106 of the ALUs. Therefore, a configuration for computing another operation may be formed by using the lines. As described above, a reconfigurable architecture is architecture capable of performing a new operation by changing a hardware configuration after fabrication.
In FIG. 1, data is input to an ALU one bit at a time. This kind of reconfigurable architecture is called as a fine grained array. If data is input to a processing element by units of one word at a time, we call this kind of reconfigurable architecture a coarse grained array (CGA).
FIG. 2 is a diagram illustrating an example of a related art tightly-coupled coarse grained array architecture.
A coarse grained array 210 includes a plurality of processing elements 211. Each of the plurality of processing elements 211 includes a function unit (FU) 212 and a register file (RF) 213. The function unit 212 performs computations, and the register file 213 is a group of registers temporarily storing data used by the function unit 212.
A configuration memory 220 stores information associated with a configuration of the coarse grained array 210. According to the configuration stored in the configuration memory 220, the coarse grained array 210 changes a connection state between processing elements included in the coarse grained array 210. A data memory 230 is located outside the coarse grained array 210 and stores data.
FIG. 3 is a diagram illustrating an example of a program including a loop. Since, in the case of the loop of FIG. 3, an identical computation is repeated, if the loop is executed in a coarse grained array, a total processing efficiency is increased.
However, when an interrupt request occurs while a loop operation is executed in the coarse grained array, it is difficult to process the interrupt. When an interrupt request occurs in a general computer architecture, a current context including a currently stored value is stored in a memory, a processing according to the interrupt is performed, the context stored in the memory is restored, and an operation originally executed is restarted. Namely, if an interrupt request occurs, a context switching may be required. The context indicates a current state and condition of a system and may include values stored in a register.
However, since the coarse grained array includes many register files as shown in FIG. 2, to store the values stored in the many register files in a memory, an amount of overhead becomes very large. Namely, it takes a relatively long time to store the values stored in the many register files to the memory. Also, to include a line for connecting each of the register files to a data memory, an overall design is very complex. As described above, the related art technology cannot provide any solution for a considerable overhead occurring in the coarse grained array to process the interrupt requiring the context switch. Particularly, it becomes more critical when a process to be performed by an interrupt has a constraint that the process must be performed in real-time.
Accordingly, a method of efficiently processing an interrupt occurring in a processor including a coarse grained array is required.